View M24L416256DA-60BIG_4567248.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

esmt m24l416256da elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.5 1/15 psram 4-mbit (256k x 16) pseudo static ram features ? advanced low-power architecture ?high speed: 55 ns, 60 ns and 70 ns ?wide voltage range: 2.7v to 3.6v ?typical active current: 1 ma @ f = 1 mhz ?low standby power ?automatic power-down when deselected functional description the m24l416256da is a high-performance cmos pseudo static ram (psram) organized as 256k words by 16 bits that supports an asynchronous memory interface. this device features advanced circuit design to provide ultra-low active current. this is ideal for portable applications such as cellular telephones. the device can be put into standby mode reducing power consumption dramatically when deselected ( 1 ce high, ce2 low or both bhe and ble are high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected ( 1 ce high, ce2 low, oe is high), or during a write operation (chip enabled and write enable we low). reading from the device is accomplished by asserting the chip enables ( 1 ce low and ce2 high) and output enable( oe ) low while forcing the write enable ( we ) high. if byte low enable ( ble ) is low, then data from the memory location specified by the address pins a0 through a17 will appear on i/o 0 to i/o 7 . if byte high enable ( bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table for a complete description of read and write modes.
esmt m24l416256da elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.5 2/15 pin configuration[3, 4, 5] 44-pin tsopii top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a4 a3 a2 a1 a0 ce1 i/o0 i/o1 i/o2 i/o3 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a5 a6 a7 oe bhe ble i/o15 i/o14 i/o13 i/o12 v cc v ss i/o4 i/o5 i/o6 i/o7 we a16 a15 a14 a13 a12 v ss v cc i/o11 i/o10 i/o9 i/o8 ce2 a8 a9 a10 a11 a17
esmt m24l416256da elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.5 3/15 product portfolio power dissipation operating, icc (ma) v cc range(v) f = 1 mhz f = f max standby, isb2 (a) product min. typ. max. speed (ns) typ.[2] max. typ.[2] max. typ.[2] max. 55 60 14 22 m24l416256da 2.7 3.0 3.6 70 1 5 8 15 17 40 notes: 2.typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc (typ) and t a = 25c. 3.ball h1, g2, h6 are the address expansion pins for the 8-mb, 16-mb, and 32-mb densities, respectively. 4.nc ?no connect??not connect ed internally to the die. 5.dnu (do not use) pins have to be left floating or tied to v ss to ensure proper application.
esmt m24l416256da elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.5 4/15 maximum ratings (above which the useful life may be impaired. for user guide-lines, not tested.) storage temperature ................ .................?65c to +150c ambient temperature with power applied ........... ............. .............. ........?55c to +125c supply voltage to gr ound potentia l ................ ? 0.4v to 4.6v dc voltage applied to outputs in high-z state[6, 7, 8] ....................................... ? 0.4v to 3.7v dc input voltage[6, 7, 8] ........... .............. ........... ? 0.4v to 3.7v output current into outputs (low) ............................20 ma static discharge voltage ...... ................ .......... ......... > 2001v (per mil-std-883, method 3015) latch-up current ....... ............. .............. .............. ....> 200 ma operating range range ambient temperature (t a ) v cc extended ? 25c to +85c 2.7v to 3.6v industrial ? 40c to +85c 2.7v to 3.6v dc electrical characteristics (over the operating range) -55, 60, 70 parameter description test conditions min. typ.[2] max. unit v cc supply voltage 2.7 3.0 3.6 v v oh output high voltage i oh = ? 0.1 ma v cc ? 0.4 v v ol output low voltage i ol = 0.1 ma 0.4 v v ih input high voltage 0.8 * v cc v cc + 0.4 v v il input low voltage f = 0 -0.4 0.62 v i ix input leakage current gnd v in vcc -1 +1 a i oz output leakage current gnd v out v cc ? 0.2v, ce2 v cc ? 0.2v, v in v cc ? 0.2v, ce2 v cc ? 0.2v or v in 0.2v, f = 0, v cc = 3.6v 17 40 a capacitance[9] parameter description test conditions max. unit c in input capacitance 8 pf c out output capacitance t a = 25c, f = 1 mhz v cc = v cc(typ) 8 pf thermal resistance[9] parameter description test conditions vfbga unit ja thermal resistance (junction to ambient) 55 c/w jc thermal resistance (junction to case) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 17 c/w notes: 6.v ih(max) = v cc + 0.5v for pulse durations less than 20 ns. 7.v il(min) = ?0.5v for pulse durations less than 20 ns. 8.overshoot and undershoot s pecifications are characteri zed and are not 100% tested. 9.tested initially and after design or process changes that may affe ct these parameters.
esmt m24l416256da elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.5 5/15 ac test loads and waveforms parameters 3.0v v cc unit r1 22000 ? r2 22000 ? r th 11000 ? v th 1.50 v switching characteristics (over the operating range)[10] ?55 ?60 ?70 prameter description min. max. min. max. min. max. unit read cycle t rc read cycle time 55 [14] 60 70 ns t aa address to data valid 55 60 70 ns t oha data hold from address change 5 8 10 ns t ace 1 ce low and ce2 high to data valid 55 60 70 ns t doe oe low to data valid 25 25 35 ns t lzoe oe low to low z[11, 12] 5 5 5 ns t hzoe oe high to high z[11, 12] 25 25 25 ns t lzce 1 ce low and ce2 high to low z[11, 12] 5 5 5 ns t hzce 1 ce high and ce2 low to high z[11, 12] 25 25 25 ns t dbe ble / bhe low to data valid 55 60 70 ns t lzbe ble / bhe low to low z[11, 12] 5 5 5 ns t hzbe ble / bhe high to high-z[11, 12] 10 10 25 ns t sk [14] address skew 0 5 10 ns write cycle[13] t wc write cycle time 55 60 70 ns t sce 1 ce low and ce2 high to write end 45 45 60 ns t aw address set-up to write end 45 45 55 ns t ha address hold from write end 0 0 0 ns t sa address set-up to write start 0 0 0 ns notes: 10. test conditions assume signal transition time of 1 v/ns or higher, timing reference levels of v cc(typ) /2, input pulse levels of 0v to v cc(typ) , and output loading of the specified i ol /i oh and 30-pf load capacitance. 11. t hzoe , t hzce , t hzbe and t hzwe transitions are measured when the outputs enter a high-impedance state. 12. high-z and low-z parameters are char acterized and are not 100% tested. 13. the internal write time of the memory is defined by the overlap of we , 1 ce = v il , ce2 = v ih , bhe and/or ble =v il . all signals must be active to initiate a wr ite and any of these signals can terminate a write by going inactive. the data input set-up and hold timing should be referenced to the edge of the signal t hat terminates write. 14. to achieve 55-ns performance, the read access should be ce controlled. in this case t ace is the critical parameter and t sk is satisfied when the addresses are stable prior to chip enable goi ng active. for the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.
esmt m24l416256da elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.5 6/15 switching characteristics (over the operating range)[10] (continued) ?55 ?60 ?70 prameter description min. max. min. max. min. max. unit t pwe we pulse width 40 40 45 ns t bw ble / bhe low to write end 50 50 55 ns t sd data set-up to write end 25 25 25 ns t hd data hold from write end 0 0 0 ns t hzwe we low to high z[11, 12] 25 25 25 ns t lzwe we high to low z[11, 12] 5 5 5 ns switching waveforms read cycle 1 (address transition controlled)[14, 15, 16] read cycle 2 ( oe controlled)[14, 16] notes: 15.device is continuously selected. oe , ce = v il . 16. we is high for read cycle.
esmt m24l416256da elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.5 7/15 switching waveforms (continued) write cycle no. 1( we controlled)[12, 13, 17, 18, 19] notes: 17.data i/o is high impedance if oe > v ih . 18.if chip enable goes in active simultaneously with we =high, the output remains in a high-impedance state. 19.during the don?t care period in the data i/o waveform, the i/os are in output state and input si gnals should not be applied.
esmt m24l416256da elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.5 8/15 switching waveforms (continued) write cycle 2 ( 1 ce or ce2 controlled)[12, 13, 17, 18, 19] write cycle 3 ( we controlled, oe low)[18, 19]
esmt m24l416256da elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.5 9/15 switching waveforms (continued) write cycle no. 4 ( bhe / ble controlled, oe low)[18, 19]
esmt m24l416256da elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.5 10/15 avoid timing esmt pseudo sram has a timing which is not s upported at read operation, if your syst em has multiple invalid address signal shorter than trc during over 15 s at read operation shown as in abnormal timing, it requires a normal read timing at leat during 15 s shown as in avoidable timing 1 or toggle 1 ce to high ( R t rc ) one time at least shown as in avoidable timing 2. abnormal timing avoidable timing 1 avoidable timing 2 ce1 15 s R we address t rc ce1 15 s R we address t R rc ce1 15 s R we address t rc t R rc
esmt m24l416256da elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.5 11/15 truth table[20] 1 ce ce2 we oe bhe ble inputs/outputs mode power h x x x x x high z deselect/power-down standby (i sb ) x l x x x x high z deselect/power-down standby (i sb ) x x x x h h high z deselect/power-down standby (i sb ) l h h l l l data out (i/o 0 ?i/o 15 ) read (upper byte and lower byte) active (i cc ) l h h l h l data out (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z read (upper byte only) active (i cc ) l h h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z read (lower byte only) active (i cc ) l h h h l l high z output disabled active (i cc ) l h h h h l high z output disabled active (i cc ) l h h h l h high z output disabled active (i cc ) l h l x l l data in (i/o 0 ?i/o 15 ) write (upper byte and lower byte) active (i cc ) l h l x h l data in (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z write (lower byte only) active (i cc ) l h l x l h data in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z write (upper byte only) active (i cc ) note: 20.h = logic high, l = logic low, x = don?t care. ordering information speed (ns) ordering code package type operating range 55 m24l416256da-55beg 48-ball very fine pitch bga (6.0 x 8.0 x 1.0 mm) (pb-free) extended 60 m24l416256da-60beg 48-ball very fine pitch bga (6.0 x 8.0 x 1.0 mm) (pb-free) extended 70 m24l416256da-70beg 48-ball very fine pitch bga (6.0 x 8.0 x 1.0 mm) (pb-free) extended 55 m24l416256da-55teg 44-pin tsopii (pb-free) extended 60 m24l416256da-60teg 44-pin tsopii (pb-free) extended 70 m24l416256da-70teg 44-pin tsopii (pb-free) extended 55 m24l416256da-55big 48-ball very fine pitch bg a (6.0 x 8.0 x 1.0 mm) (pb-free) industrial 60 M24L416256DA-60BIG 48-ball very fine pitch bg a (6.0 x 8.0 x 1.0 mm) (pb-free) industrial 70 m24l416256da-70big 48-ball very fine pitch bg a (6.0 x 8.0 x 1.0 mm) (pb-free) industrial 55 m24l416256da-55tig 44-pin ts opii (pb-free) industrial 60 m24l416256da-60tig 44-pin ts opii (pb-free) industrial 70 m24l416256da-70tig 44-pin ts opii (pb-free) industrial
esmt m24l416256da elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.5 12/15 package diagram 48-ball vfbga (6 x 8 x 1 mm)
esmt m24l416256da elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.5 13/15 44-lead tsop(ii) psram(400mil) symbol dimension in mm dimension in inch min norm max min norm max a 1.20 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.00 1. 05 0.037 0.039 0.042 b 0.30 0.45 0.012 0.018 b1 0.30 0.35 0. 40 0.012 0.014 0.016 c 0.12 0.21 0.005 0.008 c1 0.10 0.16 0.004 0.006 d 18.28 18.41 18.54 0.720 0.725 0.730 zd 0.805 ref 0.0317 ref e 11.56 11.76 11 .96 0.455 0.463 0.471 e1 10.03 10.16 10. 29 0.395 0.400 0.4 l 0.40 0.59 0.69 0.016 0.023 0.027 l1 0.80 ref 0.031 ref e 0.80 bsc 0.0315 bsc 0 8 0 8
esmt m24l416256da elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.5 14/15 revision history revision date description 1.0 2007.07.04 original 1.1 2007.11.20 modify the descriptive error for standby mode, t hzwe and t lzwe description 1.2 2007.11.22 modify t hzbe and t lzbe descriptive and restore t hzwe and t lzwe description 1.3 2008.02.27 1.add 44-pin tsopii package 2. add avoid timing 1.4 2008.03.24 add i-grade for tsopii package 1.5 2008.07.04 1. move revision history to the last 2. modify voltage range 2.7v~3.3v to 2.7v~3.6v 3. add industrial grade for bga package
esmt m24l416256da elite semiconductor memory technology inc. publication date : jul. 2008 revision : 1.5 15/15 important notice all rights reserved. no part of this document may be reproduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this document are believed to be accurate at the time of publication. esmt assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. the information contained herein is presented only as a guide or examples for the application of our products. no responsibility is assumed by esmt for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. no license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of esmt or others. any semiconductor devices may have inherently a certain rate of failure. to minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. esmt's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.

▲Up To Search▲

Price & Availability of M24L416256DA-60BIG

	To Download M24L416256DA-60BIG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .